1. Field of the Invention
The present invention relates generally to time-interleaved signal converter systems.
2. Description of the Related Art
Analog-to-digital converters, each with a converter sample rate RC, have been arranged in time-interleaved converter systems to thereby obtain a greater system sample rate RS. Although time-interleaved converter systems can thus increase the speed of signal conversion, their successful realization must often resolve hardware limitations that degrade the accuracy of the system's digital output sequences.
A significant one of these limitations concerns timing skews in the samples of the analog input signal which each converter subsequently processes. These timing skews generally arise because of input signal path differences between a system input port and each converter's input sampler and/or signal path differences between the samplers and a clock generator that is clocking them.
Timing skews have been found to generate spurious tones that degrade a system's performance. The timing skews can be determined by various means such as storing known timing skews for subsequent use in the system and estimating the timing skews with various conventional algorithms. Some algorithms require the insertion of a calibration signal (e.g., a sinusoidal signal or a ramp signal) into the system input.